如何在modelsim仿真中連接兩個設計單元

[英]How can I connect two design units in modelsim simulation


I am trying to simulate two design units in modelsim without a common testbench. The two design units are a processor and an I/O device. I have written the processor and the I/O device is an IP core from Altera.

我試圖在不使用通用測試平台的情況下模擬modelsim中的兩個設計單元。兩個設計單元是處理器和I / O設備。我編寫了處理器,I / O設備是Altera的IP內核。

I need to verify that their interfaces match. I want to leave out a common testbench because it is much faster to write a small and simple testbench in tcl(do).

我需要驗證他們的接口是否匹配。我想省略一個通用的測試平台,因為在tcl(do)中編寫一個小而簡單的測試平台要快得多。

I found out that modelsim can simulate two design units at the same time, by starting the simulation with:

我發現modelsim可以同時模擬兩個設計單元,通過以下方式開始模擬:

vsim -i work.myProcessor work.AlteraIODevice

Can anyone tell me how I can connect two signal such that a signal from one entity drives the signal of the other entity? I think this is a very quick and powerful way of doing very basic testing.

任何人都可以告訴我如何連接兩個信號,以便來自一個實體的信號驅動另一個實體的信號?我認為這是進行非常基本測試的一種非常快速有效的方法。

I imagine that connecting two signal would be something like this:

我想連接兩個信號將是這樣的:

force -drive /myProcessor/signalX /AlteraIODevice/signalY

But I have not been able to find any documentation on this matter. I hope this makes sense.

但我無法找到有關此事的任何文件。我希望這是有道理的。

1 个解决方案

#1


While force command can be used to drive signals, the examine command can be used to read. Ultimately, you'll need a Tcl script to connect both ends.

雖然force命令可用於驅動信號,但可以使用examine命令進行讀取。最終,您需要一個Tcl腳本來連接兩端。

Maybe for a sanity check would be OK, but since Tcl is very slow for this purpose, I don't see much gain.

也許對於理智檢查是可以的,但是因為Tcl對於這個目的來說非常慢,所以我看不到多少收益。

Hope it helps.

希望能幫助到你。


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