I am trying to simulate two design units in modelsim without a common testbench. The two design units are a processor and an I/O device. I have written the processor and the I/O device is an IP core from Altera.
我試圖在不使用通用測試平台的情況下模擬modelsim中的兩個設計單元。兩個設計單元是處理器和I / O設備。我編寫了處理器,I / O設備是Altera的IP內核。
I need to verify that their interfaces match. I want to leave out a common testbench because it is much faster to write a small and simple testbench in tcl(do).
I found out that modelsim can simulate two design units at the same time, by starting the simulation with:
vsim -i work.myProcessor work.AlteraIODevice
Can anyone tell me how I can connect two signal such that a signal from one entity drives the signal of the other entity? I think this is a very quick and powerful way of doing very basic testing.
I imagine that connecting two signal would be something like this:
force -drive /myProcessor/signalX /AlteraIODevice/signalY
But I have not been able to find any documentation on this matter. I hope this makes sense.
force command can be used to drive signals, the
examine command can be used to read. Ultimately, you'll need a Tcl script to connect both ends.
Maybe for a sanity check would be OK, but since Tcl is very slow for this purpose, I don't see much gain.
Hope it helps.